In order to improve the power consumption and operational performance of a microelectronic system, systems have been developed than can be tuned to respond to current conditions and can thus, reduce their operational voltage at times of low utilisation to reduce their power consumption, and/or can increase their clocking frequency when critical code is not being executed to increase their speed.
If the operational voltage is reduced by too much or the clocking speed is increased by too much then errors can occur, in that a signal may not reach the output of the processing stage during the required clock cycle(s) and thus, the previous value is output rather than the current value. In order to prevent a system from being over tuned by reducing the voltage and/or increasing the clocking speed by too much devices have used adaptive techniques that use delay-chains to imitate a processor's critical-path to determine a tuning limit for the processor. By sending a signal along the imitation critical path a voltage and frequency can be determined that are sufficient for the signal to be transmitted within a clock cycle. In order to account for inter-die variations and local voltage and temperature fluctuations the imitation or replica critical path delay is over engineered. Thus, in the example shown in FIG. 1, the critical path delay is estimated as being equivalent to the delay of 11 inverters and therefore a replica delay-chain of 13 inverters is used to account for the local variations. This replica path is used to ensure that voltage and frequency values are selected that allow a signal to travel the length of this path within a clock cycle. If the values are varied so that this is no longer the case, then the system is no longer safe and values for frequency and voltage are selected to avoid this. Thus, in order to avoid errors a clocking frequency that is slightly lower and/or an operational voltage that is slightly higher than would usually be required are chosen.
Another known way of tuning a system to reduce the voltage level and/or increase the clocking frequency as required is a razor-based system produced by ARM® Limited of Cambridge England. This is a system that is designed to operate at a point beyond this estimated absolute safe limit, the system having an error detection and recovery means to recover from cases where the signal does not reach the output in time. This system has a speculation region at the end of the clock cycle during which the output signal is measured to see if it is stable. Thus, provided any output signal attains its final value within this region, this will be detected, and if this final value is not the value at the end of the clock cycle, this can be determined and corrected. As it has this error detecting and correcting capability, the system does not need to put safety margins into the clock frequency and operational voltage. In effect it can tune its operational voltage and/or frequency to be in a range where errors are unlikely but may occur. It does this by tuning these operational parameters in dependence upon a detected error rate received from the error detection circuitry and it changes the parameters to keep this error rate at a desired low value, where it calculates its optimal operating point to be.
However, a problem arises if the error-rate drops to a very low rate due, for example, to a processor's critical paths not currently being used. This can lead to the operational voltage being scaled down and/or the frequency being increased to such levels that when the processor resumes executing critical code, it experiences significant slow-down due to very high error rates initially. In the worst case these parameters may be scaled to such an extent that the errors occur beyond the error detection or speculation window, which means they can no longer be detected or recovered from and this therefore leads to system failure.